1. Field of the Invention
The invention is generally related to floating gate memory devices such as EEPROMs and more specifically to a method for erasing flash EEPROMs arrays.
2. Description of the Relevant Art
There is a class of nonvolatile memory devices known as "flash EEPPROM's" (electrically erasable programmable read only memory devices). The operation and structure of such devices is discussed in U.S. Pat. No. 4,698,787 issued Oct. 6, 1987, to Mukherjee et al., the disclosure of said patent being incorporated herein by reference. Another discussion respecting the operation and structure of flash EEPROM devices may be found in IEEE Journal of Solid State Circuits, Vol. SC-22, No. 5, October, 1987, pages 676-683 in an article entitled "A 128K Flash EEPROM Using Double-Polysilicon Technology" by Gheorghe Samachisa, et al., the disclosure of said article being incorporated herein also by reference. A key feature of "flash" EEPROM's which distinguishes them from standard EEPROM's is that a select transistor is not included on a one-for-one basis with each floating gate transistor to select one memory cell for erasing. Instead, the memory cells of a flash EEPROM chip are erased in bulk (i.e., either the entire chip or by paged groups each having a large number of floating gate transistors). Elimination of the select transistor allows for smaller cell size and this gives the flash EEPROM an advantage in terms of manufacturing yield over a comparably sized (in terms of memory capacity) standard EEPROM.
A plurality of flash EEPROM cells may be formed on a semiconductor substrate (i.e., a silicon die) to each comprise a N-type source region integrally formed within a P portion of the substrate, a N-type drain region integrally formed within the P substrate portion and spaced apart from the source region, a P-type channel region interposed between the source and drain regions, a floating gate electrode insulatively spaced by a short distance (i.e., 100 .ANG.) above at least one of the source and drain regions, and a control gate electrode insulatively disposed above the floating gate electrode.
According to conventional operation, a flash EEPROM memory cell is "programmed" by inducing hot electron injection from a portion of the substrate (i.e., a channel section near the drain region) to the floating gate. Electron injection carries negative charge into the floating gate. This injection mechanism is normally induced by grounding the source region and a bulk portion of the substrate, applying a relatively high positive voltage to the control electrode (i.e., +12 volts) to create an electron attracting field and applying a positive voltage of moderate magnitude (i.e., approximately +6 V to +9 V) to the drain region (derived from a V.sub.pp programming pin as shown in FIG. 1B) in order to generate "hot" (high energy) electrons. After sufficient negative charge accumulates on the floating gate, the negative potential of the floating gate raises the threshold voltage of its field effect transistor (FET) and inhibits current flow through the channel during a subsequent "read" mode. The magnitude of the read current is used to determine whether an EEPROM cell is programmed or not. Typically, in the read mode, +2 V is applied to the drain, +5 V is applied to the control electrode and 0 V is applied to the source region of the memory cell.
In flash EEPROM arrays, all cells are usually erased simultaneously. This is because their source regions are all tied to a common source line. A relatively high positive voltage (i.e., +12 volts) which is derived from the V.sub.pp pin (FIG. 1B) is applied to the common source line during erasure. The control electrode and bulk substrate are grounded. The drain region is allowed to float. A strong electric field develops between the floating gate and source region, and negative charge is extracted from the floating gate to the source region by way of Fowler-Nordheim (F-N) tunneling. The dielectric spacing between the floating gate and source region (or drain region if F-N erasure is to be obtained through the drain) must be relatively small (i.e., around 100 .ANG. or less of oxide) to permit such F-N mediated deprogramming (erasure) of the floating gate electrode.
A number of drawbacks may be associated with the conventional way in which flash EEPROM cells are erased. First, because different voltages, i.e., +6 V to +9 V, +5 V and 12 V, need to be applied to the drain and source regions of the device during programming, reading and erasure; it is often necessary to provide two off-chip power supplies for operating integrated circuit chips having such flash EEPROM's cells. There is a long-felt desire within the industry to develop a flash EEPROM integrated circuit chip which may be operated from only one power supply, i.e., +5 volts. Unfortunately, the magnitude of source to substrate current tends to be relatively high during erasure, on the order of approximately 1 microamp per cell, and as a result, the power requirement of a memory chip having one million or more memory cells (a 1 megabit chip) can be as high as one ampere. Self-limiting techniques are often used for reducing this source to substrate current to levels of approximately 20 to 30 milliamps, but even at these levels, it is difficult to provide enough current from an on-chip charge pump circuit. An external power source of approximately +12 V or higher is needed.
A second drawback of the conventional erase technique arises from the fact that a relatively high reverse voltage is generated between the source and substrate during erasure. (The P type substrate is at 0 V and the N type source region is at +12 V). A double-diffused source structure is normally employed (such as disclosed in Mukherjee, 4,698,787) to protect against undesirable reverse voltage breakdown of the source to substrate PN junction. The double-diffused source structure occupies more substrate area than would otherwise be occupied by a single-diffused source structure and accordingly it is difficult to provide high density flash EEPROM cell arrays on relatively small dies in a cost-effective manner.
A third drawback associated with the conventional erasure of flash EEPROM's wherein a relatively high positive voltage (i.e., +12 V) is developed at the source region, is that there is a substantial probability that high energy holes ("hot" holes generated by a so called "avalanche effect") might be formed at a surface portion of the source to substrate junction and that these holes will become trapped in the thin dielectric underlying the floating gate. To a smaller extent, there is a further danger that additional high energy holes will be generated by a so called "band to band conduction" mechanism and these will also be trapped in the gate dielectric. The distinction between avalanche generated holes and band to band generated is discussed in an IEEE paper entitled "Drainholes Avalanche and Hole-Trapping Induced Gate Leakage in Thin-Oxide MOS Devices" by Chi Chang, et al., IEEE Electron Device Letters, Vol. 9, No. 11, November, 1988, pp. 588-590. This article is incorporated herein by reference.
The production of avalanche generated holes at the surface of the dielectric below the floating gate is undesirable because it can interfere with reliable programming, reading and erasure of randomly located memory cells (i.e., the gate disturb phenomenon), because it tends to decrease the charge retention time of the floating gate (holes trapped in the gate dielectric can migrate upwardly into the floating gate to neutralize the negative program charges in the floating gate). Specifically, during erasure, some memory cells may produce more hot holes than others and consequently their floating gates will be discharged at a faster rate. This creates a non-uniform erasure throughout the memory chip. Those holes which do not migrate to the floating gate during erasure can remain in the dielectric for random periods of time and then migrate to the floating gate, where they neutralize charge that is to be retained. Furthermore, during programming, trapped holes in the dielectric can cause undesirable programming of nonselected cells. These undesirable phenomena are further described in an article entitled "Degradations Due to Hole Trapping in Flash Memory Cells" by Sameer Haddad et al., IEEE Electron Device Letters, Vol. 10, No. 3, March, 1989, pages 117-119; said article being incorporated herein by reference. A further disadvantage of operation in the avalanche breakdown region is that it increases the magnitude of source current during erasure.